1. Field of the Invention
This invention relates to a semiconductor integrated circuit (hereinafter also called "IC"), and more particularly to a concept of reducing the possibility of a parasitic diode in an IC having an element isolating structure.
2. Description of the Related Art
FIG. 5 of the accompanying drawings is a cross-sectional view showing a typical IC. The IC has a PNP bipolar transistor 10 formed in a P substrate 12.
in the P substrate 12, an N.sup.+ implanted layer 16 is formed by, for example, ion implantation. Formed over the N.sup.+ implanted layer 16 is a P.sup.+ layer 18 on which an N epitaxial layer 20 is formed. An N.sup.+ layer 22 and a P layer 24 are formed in the N epitaxial layer 20. The PNP transistor 10 consists of the P.sup.+ layer 18, the N epitaxial layer 20 and the P layer 24 as the collector layer, base layer and emitter layer, respectively. The N.sup.+ layer 22 is the base contact layer of the PNP transistor 10.
The PNP transistor 10, around which an N expitaxial layer 26 is formed, is contiguous to other elements ( such as transistors and diodes) via a diffusion layer 28. Only parts (N epitaxial layers 30 and 32) of the other elements contiguous to the PNP transistor 10 are illustrated in FIG. 5. The diffusion layer 28 is a so-called element-isolating layer for electrically isolating the PNP transistor 10 from the other elements horizontally in FIG. 5 and may be extensively used in circuit-isolation.
in the manufacture of the IC of FIG. 5, the foregoing layers 14 through 32 are formed in the P substrate 12, and then an insulating film 34 is formed in a predetermined pattern on the surface of the P substrate 12. If silicon is used as the substance of the P substrate 12, the insulating film 34 is usually formed by a surface oxidation process. The insulating film 34 to be obtained by the surface oxidation process is a silicon oxide film. Upon forming the silicon oxide film 34, a conductive layer is formed in a predetermined pattern on the top surface of the P substrate 12. The substance of the conductive layer is usually metal.
Part of the conductive layer pattern is used as a collector electrode 36, a base electrode 38 or an emitter electrode 40 of the PNP transistor 10. The collector electrode 36, the base electrode 38 and the emitter electrode 40 are formed respectively on the collector layer 18, the base layer 20 via the base contact layer 22, and the emitter layer 24. A collector terminal 42, a base terminal 44 and an emitter terminal 46 are connected to the collector electrode 36, the base electrode 38 and emitter electrode 40, respectively.
Part of the conductive layer pattern is used in applying a supply voltage to the N epitaxial layer 26 and connecting the element-isolating layer 28 to ground; that is, a positive d.c. voltage from a battery 50 is applied to the conductive layer 48 formed on the N epitaxial layer 26, and on the other hand, a conductive layer 52 formed on the element-isolating layer 28 is grounded. Therefore the junction between the N epitaxial layer 26 and the element-isolating layer 28 is reverse biased. The N.sup.+ implanted layer 16 has the same potential as that of the conductive layer 52; therefore the junction between the N+ implanted layer 16 and the P substrate 12 is reverse biased. As a result, a current will stop flowing through these PN junctions; that is, as the result that these PNP junctions become insulate, the PNP transistor 10 will be electrically isolated from the elements contiguous to it. Usually a positive d.c. voltage is also applied to the N epitaxial layer 30, 32. In the case of a double-power-source-driven IC, the reverse biasing may be performed by either the positive power source or the negative power source.
Thus the N layer 26 around the PNP transistor 10 is essential to element isolation using the element-isolating layer 28, but the junction between the N epitaxial layer 26 and the collector layer 18 functions as a parasitic diode. FIG. 6 shows a parasitic diode 54 formed by this junction. As shown in FIG. 6, the junction between the N epitaxial layer 26 and the collector layer 18 forms a PN diode (i.e., the parasitic diode 54) connected to the collector of the PNP transistor 10. The parasitic diode 54 functions in an electrostatic capacity between the collector of the PNP transistor 10 and the battery 50. This electrostatic capacity would generally affect the frequency characteristic of the circuit. In fact, the junction between the N epitaxial layer 26 and the element-isolating layer 28 also functions as a parasitic diode, but this diode does not contribute to circuit operation; therefore this diode is omitted in FIG. 6 and the following description. "The diode does not contribute to" means that it does not appear on an equivalent circuit showing the connections between the individual elements formed in the P substrate 12.